The present invention relates to multi-bit-per-cell flash memories and, more particularly, to a method of optimizing read reference voltages for a multi-bit-per-cell flash memory.
Originally, flash memories stored only one bit per cell. Flash memories that store two bits per cell now are available commercially, and flash memories that store more than two bits per cell are being developed. Conventionally, flash memories that store one bit per cell are called “Single Level Cell” (SLC) memories and flash memories that store more than one bit per cell are called “Multi Level Cell” (MLC) memories. This nomenclature is misleading because the cells of a SLC memory actually have two levels, for indicating whether the single bits stored therein are “1” bits or “0” bits. Therefore, these two kinds of flash memories are referred to herein as “Single Bit Cell” (SBC) memories and “Multi Bit Cell” (MBC) memories.
FIG. 1 illustrates how a bit pattern of three bits is stored in a MBC memory that is capable of storing three bits per cell.
The threshold voltage of a flash cell is in a range, called the “voltage window”, from a minimum value Vmin to a maximum value Vmax. For historical reasons, writing data to a flash cell is called “programming” the flash cell. (The terms “writing” and “programming” are used interchangeably herein.) This is done by applying voltage pulses to the cell, to inject electrons from the cell's silicon substrate through the cell's oxide layer into the cell's floating gate, until the threshold voltage of the cell is high enough within the voltage window to represent the desired bit pattern. In a three-bit-per-cell memory, the voltage window is divided into eight voltage bands: from Vmin to V1, from V1 to V2, from. V2 to V3, from V3 to V4, from V4 to V5, from V5 to V6, from V6 to V7 and from V7 to Vmax. A threshold voltage within one of the voltage bands represents a bit pattern as shown in FIG. 1: a threshold voltage between Vmin, and V1 represents the bit pattern “111”, a threshold voltage between V1 and V2 represents the bit pattern “110”, etc. In general, the voltage window of a m-bit-per-cell memory is divided into 2m voltage bands.
To read a flash cell, the threshold voltage of the flash cell is compared to the reference voltages that define the voltage bands. In the case of some flash memories (hereinafter called “type 1” memories), reading a cell that stores a bit pattern of in bits requires m such comparisons. For example, when m=3, as illustrated in FIG. 1, the threshold voltage first is compared to V4. Depending on the outrcome of that comparison, the threshold voltage is compared to either V2 or V6. Depending on the outcome of the second comparison, the threshold voltage is compared to either V1 or V3 or V5 or V7. Note that this comparison does not assume prior knowledge of the threshold voltage: circuitry in the flash memory returns a signal indicating whether the threshold voltage is higher or lower than the reference voltage to which it is being compared.
In the case of some other flash memories (hereinafter called “type 2 memories”), the threshold values of all the cells that are read collectively are compared to all 2m−4 reference voltages between Vmin and Vmax.
In a collection of flash cells, the threshold voltages of the cells are distributed statistically around the centers of their respective voltage bands. FIG. 1 shows the threshold voltages in the first voltage band distributed according to a distribution curve 10, the threshold voltages in the second voltage band distributed according to a distribution curve 12, the threshold voltages in the third voltage band distributed according to a distribution curve 14, the threshold voltages in the fourth voltage band distributed according to a distribution curve 16, the threshold voltages in the fifth band distributed according to a distribution curve 18, the threshold voltages in the sixth band distributed according to a distribution curve 20, the threshold voltages in the seventh band distributed according to a distribution curve 22 and the threshold voltages in the eighth band distributed according to a distribution curve 24. There are several reasons for the finite widths of these distributions:
1. The programming process is a stochastic one that relies on inherently stochastic processes such as quantum mechanical tunneling and hot injection.
2. The precision of the read/program circuitry is finite and is limited by random noise.
3. In some flash technologies, the threshold voltage of a cell being read is affected by the threshold voltages of neighboring cells.
4. Chip-to-chip variations and variations in the manufacturing process cause some cells to behave differently than other cells when read/programmed.
In addition, the threshold voltage distributions tend to change over time, as follows:
1. As a flash memory is programmed and erased, the voltage window tends to shrink and the voltage bands become biased. These phenomena limit the number of times a MBC flash memory can be erased and re-programmed.
2. The threshold voltage of a flash cell that is not programmed for a long time tends to drift downward. This phenomenon limits the time that data can be reliably retained in a flash memory.
The voltage bands of a flash cell should be designed to be wide enough to accommodate all these phenomena, but not too wide. A voltage band that is too narrow, relative to the associated threshold voltage distribution curve and relative to the drift of that curve over time, leads to an unacceptably high bit error rate. Making the voltage bands very wide relative to the associated threshold voltage distributions limits the number of bits in the bit patterns that can be stored in the flash cell. In practice, flash memories are designed to have one error per 1014-1016 bits read. Some flash technologies are unable to achieve this error rate while storing the desired number of bits per cell. Some flash memories based on such technology use error correction circuits to compensate for their high intrinsic error rates. Some NAND flash manufacturers have instructed their customers to incorporate error-correcting code in their applications.
The problem of determining the optimal location of reference voltages for reading the contents of flash memory cells becomes especially acute when the number of programming levels increases. The reason for this is that when the number of levels is large, any inaccuracies in estimation of the information stored in the cells cause superfluous errors that can affect reliable performance of the memory.
The central problem in finding optimal reference voltages is that, as discussed above, the programmed threshold voltage levels are not constant, and may vary as a function of retention time, number of program/erase (P/E) cycles, as well as depend on particular production wafer, lot, chip, block, word and bit line. Therefore the behavior of a threshold voltage level programmed to a certain cell can be predicted only statistically.
As discussed above, the standard procedure for reading the contents of cells consists of comparison of the cell voltage with fixed reference voltages. The number of reference voltages is one less than the number of programming levels, as illustrated in FIG. 1, if “hard” information is used in processing (i.e. estimation of the stored bits without reference to the reliability of the estimation), otherwise the number of reference voltages is larger. See e.g. Guterman et al., U.S. Pat. No. 6,751,766 for an example of the use of more reference voltages than programming levels to estimate the reliability of read bits. U.S. Pat. No. 6,751,766 is incorporated by reference for all purposes as if fully set forth herein.
Several approaches are currently used for defining reference voltages. The simplest approach relies on placing the reference voltages at fixed voltages that are calculated based on theoretical and practical models following from measurements of is flash devices. Such models allow minimization of the error probability in determining the correct programmed voltage level.
FIG. 2 presents an example of optimization for the choice of reference voltages (vertical dashed lines) between two voltage levels. The initial probability density functions (pdf's) for four neighboring levels are presented as solid lines while the corresponding pdf's after the maximum allowed number of P/E cycles followed by the maximum allowed data retention (DR) time are depicted as dotted line.
Clearly the optimal choice of the reference voltage corresponds to the optimal choice for the pdf's after P/E and DR. However, this choice might increase the error probability for the freshly programmed flash memory. Another drawback of the described scheme is that the models yielding pdf's are not accurate and actual behavior of flash voltages can essentially differ from the behavior predicted by a model.
If P/E is the sole cause of the changes of the pdf's, the reference voltages can be corrected based on a count of P/E cycles. If DR also contributes to the changes of the pdf's, a similar correction scheme often is not possible, among other reasons because time-stamping data stored in a flash memory often is inconvenient or impossible. The so called “dynamic reading” schemes assume several attempts of placing the reference voltages starting at locations corresponding to zero DR, and followed by reference voltages situated in the range between the locations corresponding to zero DR and the location for the maximum allowed DR. The suitability of a given set of reference voltages can be evaluated using standard error detection and correction schemes to detect when there are too many errors in the data, as read according to those reference voltages, to be corrected. FIG. 3 shows two such ranges, for reference voltage Vr(i) and for reference voltage Vr(i+1), with the range for reference voltage Vr(i+1) labeled “Dynamic read range”. As in FIG. 2, the initial pdf's are solid and the final pdf's are dotted. Such a scheme is taught by Lasser in US Patent Application Publication 2007/0091677, which patent application is incorporated by reference for all purposes as if fully set forth herein.